In a conventional charge trapping dielectric flash memory device, the charge storing regions can be part of a non-conductive charge trapping layer that can be disposed between a bottom (or tunnel) dielectric layer and a top dielectric layer. This dielectric stack can be formed over a P-type silicon substrate having a first and a second bit line disposed therein. A conductive word line that can be constructed from N type or N+ type polycrystalline silicon can be formed over the dielectric stack and serves as a gate electrode. The bit lines can be formed from N+ conductivity type material. Upon application of appropriate voltages to the word line and/or the bit lines, the bit lines can respectively function as a source and a drain with a channel region defined in between.
By the appropriate application of voltage potentials to the gate electrode, the source and/or the drain, each charge storing region can be programmed to store an amount of charge corresponding to a programmed, or charged, data state (as opposed to an unprogrammed, or blank, data state). Programming of the charge storage elements can involve channel hot electron (CHE) injection. In channel hot electron injection, electrons traveling within the channel that have a sufficient amount of energy to overcome the barrier height of the tunnel dielectric layer can become injected into the charge trapping layer where they can become trapped.
A conventional charge trapping dielectric memory device with an N+ polysilicon gate electrode usually can only be erased using the conventional technique of “hot hole injection”, also referred to as band-to-band (BTB) hot hole injection. In hot hole injection, a gate voltage of approximately −4 to −8 volts can be applied along with a drain voltage on the order of 4.5 to 6.0 volts, while the source can be floated or grounded to erase one of the charge storing elements. Conversely, in order to erase the other charge storing element, the drain can be floated and appropriate voltages can be applied to the source and the gate electrode.
With such erase conditions, a BTB tunnel current can be created under the gate. Holes can be generated under these conditions and accelerate from the N-type drain region into the P-type body. The generated holes can be accelerated in the electrical field created near the P-N drain/body junction. Some of the holes can surmount the oxide to silicon interface between the substrate and the bottom oxide and can be injected into the nitride charge storing layer to displace electrons and erase the cell.
However, as the hot holes are created in the interface between the substrate and the bottom tunnel oxide, the interface and the bottom tunnel oxide can become damaged. Eventually, this damage can lead to data retention problems. As an example, degraded data retention reliability over program/erase cycling can occur due to stored charge leakage through the damaged tunnel oxide. As a result, a charge amount that has been “programmed” into one or both of the charge trapping regions can be reduced over time. In certain circumstances, enough charge can be lost that the data retention capability of the memory cell can be compromised.
Fowler-Nordheim erase (FN erase) can be used in floating gate devices (e.g., charge is stored in a conductive polysilicon layer rather than a dielectric layer). However, FN erase can be problematic for conventional memory cells. In particular, the vertical electric fields present during the erase can cause electrons to be pushed out from the charge storing layer to the substrate and/or cause electrons to flow from the N+ gate electrode through the top oxide and into the charge storing layer at approximately the same tunneling rate. Therefore, while there can be a net current from the gate electrode to the substrate, charge is not always erased effectively from the charge storing layer.
It is desirable to prevent the flow of electrons from the gate electrode to the charge storing layer during FN erase. It is also be desirable to lower the voltage level applied to effectuate an FN erase.